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LOCAL BUS SINGLE-STROBE TRANSFER
System Interfaces
Local Bus Single-Strobe Transfer
T4 T1
LOCAL BUS SINGLE-STROBE TRANSFER
T4
HCS HCS
HCS
HA[3:0] –0]
HA[3:0]
HA_DSP0
HA_DSP0
T1
T2
T2
T6
T3
T3
HDS
HDS
HDS
HRW HRW
T5
T5
T7
T6
T11
T10
T11
T8
T8
HRW
HD[15–0]
HD[15:0]
T7
T12
T10
Write
HD[15:0]
HD[15:0]
HD[15–0]
HD[15:0]
Read
WRITE
WRITE
READ
READ
T12
T9
T9
Figure 4. Bus Transfer Timing Diagram
The CPLD contains registers for controlling and/or sampling several board signals. These signals include
reset, power and LED control, and interrupts. Consult Section 7 , CPLD Registers, on page 25 and the
board schematics for information on signals controlled or sampled by the CPLD registers.
Table 3. Bus Transfer Timing Intervals
Description
Address set-up before the chip select
Chip-select set-up before the data strobe
Chip-select hold after the data strobe
Address hold after the chip select
Write data set-up before the data strobe assertion
Data strobe width
HRW set-up before the data strobe
Data strobe after the data strobe
Read data hold after the data strobe deassertion
Write data hold after the data strobe deassertion
HRW hold after the data strobe
Read data valid after the data strobe assertion
2.2
Ethernet (MII/RMII)
Key
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Minimum
10 ns
10 ns
10 ns
0 ns
10 ns
40 ns
10 ns
20 ns
10 ns
5 ns
10 ns
30 ns
Two media-independent interfaces (MII) and three reduced MII (RMII) are available for connection to an
external host board at the CMC connectors. All four MSC711x devices connect to separate full duplex
RMII ports of the on-board ten-port Ethernet switch. One full duplex RMII port from the switch connects
to J3 of the PDK CMC site. Two full duplex RMII ports for the switch connect to J8 of the MDS CMC
site. Figure 5 shows a diagram of the Ethernet switch port connections on the board. The switch is
configured through its CPU bus interface (see Figure 3 ).
MSC711x Packet Telephony Farm Card (SPT711xPFCE), Rev. 1
6
Freescale Semiconductor
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